The invention relates to a self configuring speed path for use in a microprocessor having a multiple clock frequency option. More specifically, the instant invention relates to a reconfigurable speed path which is responsive to a clock select signal in a multiple clock microprocessor to configure the speed path for use with a clock signal having a higher frequency than the speed path's normal operational capability.
In microprocessors having multiple clock options, an external clock at a first frequency, for example, 25 MHz, is applied within the microprocessor to a circuit which outputs several clock frequencies at multiples of the external clock. Thus, a clock applied to such a microprocessor has a circuit which outputs an internal clock at one of a plurality of multiples of the externally applied clock frequency. For example, a 25 MHz clock might allow the user to select an internal clock at 25 MHz, 50 MHz, or 75 MHz. The internal clock is used by individual functional circuits of the microprocessor. It generally is desirable to select the clock multiple which leads to the best overall system performance.
One problem associated with such conventional devices arises when the clock frequency is selected at one of the higher multiples, since a particular functional circuit may require more than one clock cycle to perform its function. This results in a speed path. As used herein a speed path is a path that takes longer to resolve than the other paths in the processor. Such speed paths impose a maximum limit on the processor's internal clock frequency. In order to overcome this problem considerable effort has been under taken to design faster speed paths, because the timing of the worst speed path ultimately limits the microprocessor's top operating frequency.